He ido a ver que dicen en la pagina de ARM sobre la caña que le puedo meter al reloj de la gba y he encontrado esto:
Considerations when designing with an ARM hard macro clock.
The main consideration when designing with the ARM clock should be not to violate the minimum HIGH pulse width or the minimum LOW pulse width.
Let's take the example where an ARM7TDMI has been characterised as being able to run at a maximum frequency of 90MHz.
___________ <-- 5.55ns --> __________ ___
MCLK ___/ \___________/ \__________/
<-- 5.55ns -->
Assuming that there is a 50 percent duty cycle, the minimum LOW and HIGH pulse width will be 5.55ns each.
If this clock was then run at 32MHz (31.25ns period) then there would be no problems varying the duty cycle anywhere between the two following diagrams:
________ <---------------- 25.7ns ----------------> ________
MCLK __/ \___________________________/ \_____
<-5.55ns->
__ <-5.55ns-> ___________________________ ______
MCLK \________/ \________/
<----------------- 25.7ns ----------------->
AS LONG AS YOU DO NOT VIOLATE THE MINIMUM HIGH OR LOW PULSE WIDTH OF THE CLOCK, YOU CAN HAVE ANY CLOCK DUTY CYCLE YOU WANT.
Synthesisable designs only operate off the rising edge of the clock and so are only sensitive to violating the minimum clock period. The hard macros utilise both the rising and the falling
edge of the clock and so consideration must be given to both the HIGH and LOW pulse widths.
Lastima que no tenga ni puta idea de electronica. Necesito ayuada de alguien que controle, a ver si me explica esto:
ARM hard macro clock -> se refieren al reloj que controla el procesador?
Y si es asi y suponiendo que solo hay que respetar el limite de 5.55 ns hasta donde se puede llegar? (pasan los 64 Mhz). Y si todo eso es cierto, porque a la GBA solo le pusieron 4.194 Mhz?
Dudas, dudas ...
que mierda esto se come los espacios, para ver los "diagramas" id a la pagina original:
http://www.arm.com/support.nsf/html/cores_faq!OpenDocument&ExpandSection=20