1.1 Broadway Microprocessor Overview
This section describes the features and general operation of Broadway and provides a block diagram
showing major functional units. Broadway is an implementation of the PowerPC microprocessor
family of reduced instruction set computer (RISC) microprocessors with extensions to improve the
floating point performance. Broadway implements the 32-bit portion of the PowerPC Architecture,
which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point
data types of single and double-precision. Broadway extends the PowerPC Architecture with the
paired single-precision floating point data type and a set of paired single floating point instructions.
Broadway is a superscalar processor that can complete two instructions simultaneously. It
incorporates the following six execution units:
• Floating-point unit (FPU)
• Branch processing unit (BPU)
• System register unit (SRU)
• Load/store unit (LSU)
• Two integer units (IUs): IU1 executes all integer instructions. IU2 executes all integer
instructions except multiply and divide instructions.
The ability to execute several instructions in parallel and the use of simple instructions with rapid
execution times yield high efficiency and throughput for Broadway-based systems. Most integer
instructions execute in one clock cycle. The FPU is pipelined, it breaks the tasks it performs into
subtasks, and then executes in three successive stages. Typically, a floating-point instruction can
occupy only one of the three stages at a time, freeing the previous stage to work on the next floatingpoint
instruction. Thus, three single or paired-single precision floating-point instructions can be in the
FPU execute stage at a time. Double-precision add instructions have a three-cycle latency; doubleprecision
multiply and multiply-add instructions have a four-cycle latency.
Figure 8-2. IBM Broadway Microprocessor Block Diagram on page 291 shows the parallel
organization of the execution units (shaded in the diagram). The instruction unit fetches, dispatches,
and predicts branch instructions. Note that this is a conceptual model that shows basic features rather
than attempting to show how features are implemented physically.
Broadway has independent on-chip, 32-Kbyte, eight-way set-associative, physically addressed L1
caches for instructions and data and independent instruction and data memory management units
(MMUs). The data cache can be configured as a four-way, 16-KByte locked cache and a four-way,
16-KByte normal cache. Each MMU has a 128-entry, two-way set-associative translation lookaside
buffer (DTLB and ITLB) that saves recently used page address translations. Block address translation
is done through the four-entry instruction and data block address translation (IBAT and DBAT) arrays,
defined by the PowerPC Architecture. During block translation, effective addresses are compared
simultaneously with all four BAT entries.
For information about the L1 cache, see Chapter 3, "Broadway Instruction and Data Cache
Operation".
The L2 cache is implemented with an on-chip, two-way set-associative tag memory, and an on-chip
256-Kbyte SRAM with ECC for data storage. See Chapter 9, "L2 Cache, Locked D-Cache, DMA and
Write Gather Pipe".
The Broadway has a direct memory access (DMA) engine to transfer data from the external memory
to the locked data cache and to transfer data from the locked data cache to the external memory.
A write gather pipe is implemented for effecient non-cacheable store operations.
Broadway has a 32-bit address bus and a 64-bit data bus. Multiple devices compete for system
resources through a central external arbiter. Broadway’s three-state cache-coherency protocol (MEI)
supports the modified, exclusive and invalid states, a compatible subset of the MESI
(modified/exclusive/shared/invalid) four-state protocol, and it operates coherently in systems with
four-state caches. Broadway supports single-beat and burst data transfers for external memory
accesses and memory-mapped I/O operations. The system interface is described in Chapter 7, "Signal
Descriptions" and Chapter 8, "Bus Interface Operation" in this manual.
Broadway has four software-controllable power-saving modes. Three static modes, doze, nap, and
sleep, progressively reduce power dissipation. When functional units are idle, a dynamic power
management mode causes those units to enter a low-power mode automatically without affecting
operational performance, software execution, or external hardware. Power management is described
in Chapter 10, "Power and Thermal Management" in this manual
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