Psp ganadora del premio al mejor microprocesador de bajo consumo.

Bueno, para el que no esté enterado, la revista MPR (micro processors report), una de las revistas más prestigiosas del sector, hace todos los años una lista de los mejores microprocesadores según distintas características (pc de sobremesa, servidor, empotrados...) y este año (2004) el ganador en la categoría de micros de bajo consumo han sido la pareja de mips r400 que lleva montados la psp, os pongo la parte del artículo que habla de ello y perdón por no estar traducido, o si hay muchos acrónimos sin explicar pero ando algo corto de tiempo esta semana, y podeis utilizar uno de los traductores online que hay.

Sony’s PlayStation Portable (PSP) chip is probably the
most complex chip introduced in 2004. (See MPR 9/13/04-
01, “Sony’s PSP: Maximum Technology.”) To begin with, the
chip incorporates two MIPS R4000 32-bit cores that can be
clocked between 1MHz and 333MHz, an FPU, and a VFPU
(vector FPU). One of the MIPS cores is tasked with running
the system and the game accelerators; the other controls the
media codecs. The chip’s 3D graphics performance relies on
a rendering engine and a surface engine. The graphics
engines are clocked at half the frequency of the MIPS controllers.
The chip’s audio functions are delivered by a combination
of simple DSP and reconfigurable datapath. Sony is
probably using its own V/f power manager. It resembles the
Adaptive Power Controller but was not acquired from
National Semiconductor. Sony’s PSP products, incorporating
the PSP chip, were released for sale in Japan in December
2004, reaching about 95% of absorption of available quantities
(approximately 100,000 units) within two weeks. Sony
retail stores expect the PSP to become available in the U.S.
during March.

Analysts’ Choice Award for Best Low-Power Processor
Of the two chips, Sony’s PSP shows the highest integration
and configuration aimed at obtaining very low power for
its tasks. Low power is achieved by using separately controlled
multiple programmable cores and hard-wired accelerators.
Sony’s design team took one additional step beyond
routine design by incorporating an FPGA fabric that,
through reconfiguration, can help the chip’s designers reduce
the required chip real estate and the associated power
consumption.


y para que veais la competencia que tenia una captura de la
Tabla comparativa.

Por si todavia os quedaba alguna duda acerca de si vale lo que cuesta la consola y para los que se quejan de duración de batería.