Sobre Servidor PSO y Programación en DC

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Boot ROM configuration
The Boot ROM stores the data described below. There are 2MB of ROM space. Table 5-1 contains estimates for the amounts of space used for data within the Boot ROM.

Details of the data Necessary space
IPL 0.25MB
Multi player (includes draw image/audio data) 0.75MB

Kanji Font 1MB
TOTAL 2MB
Details of the ROM data

Specifying a ROM
The ROM is a 16M bit (2MB) mask ROM with a 8 bit bus width and has an access time of 100~240ns.
The table below is the specified ROM details used by the Dreamcast system.

ROM type Mask ROM
ROM size 16Mbit
Bus width 8 bit
Access time 100ns～240ns
Table 5-2　Specifying ROM

About the access cycle to the ROM
　As stated previously the Boot ROM is located on the G1bus. With regards to the bus cycle set-up or hold of an address, reading and writing is possible. The pulse width can be specified through the HOLLY register. Regarding the number of access cycles, 1 byte, 2 byte and 4-byte access is possible.

G1 bus

The G1 bus is supported by HOLLY. The GD-ROM, system ROM, flash memory and other asynchronous devices are connected to the G1 bus in parallel. The access method used on the G1 bus differs according to the target device, with accesses to the GD-ROM device being different from accesses to system ROM or flash memory. Access is based on the ATA standard, according to a protocol that supports the ATA standard in part. One interrupt line from the GD-ROM is supported. Regarding data transfers, DMA transfers are possible in the GD-ROM area.
G1 bus

The G1 bus is connected to the GD-ROM drive and the ROM/ FLASH (space 2MB and bus width 8bit). Access to the GD-ROM uses an interface similar to EIDE (similar to ATA) but part of the bus signal line has multiplexed signal lines that are used for ROM/FLASH access. Additionally part of the address line to ROM/FLASH has multiplexed MODE signals which are incorporated in the system information. The bus operation is not synchronised and at the time of GD-ROM access the data bus width is 16 bit although at the time of ROM/FLASH access, it is 8 bit. The real transfer speed at the time of GD-ROM access is 10MB/s (2880ns/32B).

G1 bus i/f
l DMA End
l Illegal Address set
l DMA over run
l ROM/FLASH access at DMA
l From GD-ROM drive (Interruption from the GD-ROM)


This G1 bus also supports the loading of 8 bits of data (a country code) that are set on the board.

The GD-ROM drive, Boot ROM and flash memory are buses in parallel connection and the bus has a multiplexed EIDE-like i/f and Boot ROM i/f. Part of the Boot ROM address line, the 8 bit of code that contains the system data, is multiplexed. The data bus width is 16 bit at the time of GD-ROM access and 8 bit for Boot ROM and Flash memory access. It is also subject to type 1 interrupted entry from the GD-ROM.

GD-ROM access uses an ATAPI like protocol. For details of the protocol, refer to a separate document.
In order to prevent hardware reconstruction and Illegal copies, this bus is not external on commercially produced Dreamcast hardware. In the case of the SET5 set for software Development, the Crossproducts Company debugging adapter base is connected to this and thus allows software debugging. In that case, the downloading of data occurs through this bus.

4x-12xGD-ＲＯＭ
The drive reads using a CAV method and the data reading speed is 4x for normal space and 12x for high-density space. The drive has a 128KB buffer RAM and data is transferred through HOLLY. It delivers GD-DA (high-density digital audio) as opposed to AICA that is an audio IC.

This is the master/ target device of the root bus and performs the transfer between the GD-ROM drive connected to the bus and the ROM/FLASH. The data is transferred in units of 32B. There is also a DMA function.

Boot ROM
The system/boot ROM used by SH4 is connected to the G1 bus. There are 2MB of ROM space and a data bus width of 8 bit. The access time of the Dreamcast is set at 100ns.

Flash ROM
Information such as the Dreamcast system administration number is stored here.

GRESN output Reset for device
Pin name i/o Explanation
Ｇ1 bus related signals
G1D[7:0] In/output G1 data bus-lowest 8bit
G1RAD[15:8] In/output G1data bus- highest 8bitAdapted to ROM address[7:0]
G1RAL[10:8] Output ROM address[10:8]
G1MRA[18:11] In/output ModeROM address[18:11]
G1RAH[20:19] Output ROM address[20:19]
G1CS[1:0]N Output GD-ROM chip selection
G1ROMCSN Output Boot ROM chip selection
G1FMCSN output Flash memory chip selection
G1RDN output Boot ROM read signal
G1WRN output Boot ROM light signal (for Flash ROM, normally not connected)
G1IORDY input GD-ROM IO ready
G1DREQ input GD-ROM DMA request
G1DACKN output GD-ROM DMA acknowledge
G1INTRQ input GD-ROM interrupt
Pin name i/o Explanation
Ｇ2 bus related signals
G2AD[15:0] In/output Address/data multiplex bus
G2BHN output Highest data(G2AD[15:8]) valid
G2BLN output Lowest data(G2AD[7:0]) valid
G2FRN output Frame signal
G2CLK output G2bus/clock
G2TRN input /TargetReady
G2DSN In/output /DeviceSelect
G2STN Input /Stop
G2RQAICN Input AICA /TransferRequest
G2RQEX0N Input External Device0 /TransferRequest
G2RQEX1N Input External Device1 /TransferRequest
G2RQDEVN Input Debugger /TransferRequest
G2MDMCSN Output Modem chip select
G2IRAICN Input AICA interruption
G2IRMDMN Input Modem interruption
G2IREXTN Input External device interrupt

(G1 Interface... GD-ROM、System-ROM、Flash-ROM etc．)
· GD-DMA control registers
· GD-DMA secret/debug register
· G1 I/F block hardware control registers

G1 Interface
(The GD-DMA Control Registers are described below.)

SB_GDSTAR Address：0x005F 7404
bit 31-29 28-5 4-0
000 GD-DMA start address Reserved

Data transfers between the GD-ROM and the following areas are possible using ch0-DMA. This register specifies the starting address in 32-byte units. (default = 0xXXXXXX)

0x00700000~0x00707FE0 :32KByte : G2 AICA -Register
0x00800000~0x009FFFE0 :2MByte : G2 AICA -Wave Memory
0x01000000~0x01FFFFE0 :16Mbyte : G2 External Devices #1
0x02700000~0x02FFFFE0 :9MByte : G2 AICA (Image area)
0x03000000~0x03FFFFE0 :16Mbyte : G2 External Devices #2
0x04000000~0x047FFFE0 :8MByte : PowerVR Texture Memory 64bit access area
0x05000000~0x057FFFE0 :8MByte : PowerVR Texture Memory 32bit access area
0x06000000~0x067FFFE0 :8MByte : PowerVR Tex. Mem. 64bit access area (Image area)
0x07000000~0x077FFFE0 :8MByte : PowerVR Tex. Mem. 32bit access area (Image area)
0x0C000000~0x0CFFFFE0 :16Mbyte : System Memory
0x0E000000~0x0EFFFFE0 :16Mbyte : System Memory (Image area)
0x14000000~0x17FFFFE0 :64Mbyte : G2 External Devices #3

Notes:
· This register is not initialized after a power-on reset or a software reset.
· The hardware does not change the data in this register.
· For details on address mapping

G2 bus
The G2 bus is supported by HOLLY. This bus supports the audio chip AICA, a modem, external expansion devices, and other synchronous devices. The G2 bus is basically a PCI-like bus, with a bus clock of 25MHz and a bus width of 16 bits. The bus supports three interrupt lines, one for each of the supported devices listed above. Aside from the modem, DMA transfer is possible with the AICA and expansion devices.

Access Methods
Although the GD-ROM access timing is based on the ATA standard (the electrical interface conforms with ATA-3), the GD-ROM supports only the timing modes listed below. (The GD-ROM does not support "Single Word-DMA" from the ATA standard.)

This specification defines a unique disc format standard originated by Sega. A disc conforming to this specification is called a GD (Gigabyte Disc) or GD-ROM.

The audio data format recorded on the “High-Density Area” defined in this specification is called GD-DA.
The program data format recorded on the “High-Density Area” defined in this specification is called GD-ROM.
The access unit of CD blocks for program development is the “Frame Address (FAD)”.

Disc Size and Recording Time
The Single-Density Program Area holds up to 4 minutes (18,000 sectors), which equates to a data storage capacity of 36,000 KB.
The High-Density Program Area holds up to 112 minutes and 4 seconds (504,300 sectors), which equates to a data storage capacity of 1,008,600 KB.

Data in the Single-Density Area is readable by common CD players. Its format complies with the following standards:
Physical Format: ‘Red Book’ and ‘Yellow Book’
Logical Format: ISO9660
Data in the High-Density Area is readable only with special players compatible with Sega’s unique standard. Its format complies with the following standards:
Physical Format: Sega Custom Format
Logical Format: ISO9660

Data Tracks
The High-Density Program Area always begins with data track 03.
Data for Pattern I and Pattern II is allocated to track 03, while Pattern III uses at least two tracks for data: track 03 and the last track on the disc.
The data tracks for Pattern III are located nearest the outer edge of the disc for fastest access.
2 seconds of Pause at the beginning and 2 seconds of Post gap at the end of the data track are required. A data track must be at least 4 seconds long including Post gap, but excluding Pause area.
The High-Density Area data track disc format is compatible only with Mode1 format, so it does not support Mode2 format (CD-ROM XA, etc).

Audio Tracks
Audio for Pattern II may be allocated to tracks 04 to 99 consecutively; or for Pattern III, to tracks 04 to 98 consecutively.
2 seconds of pause at the beginning of each track, and 2 seconds of silent area at the end of the last audio track are required.
As shown the Index-01, 02, … , an Audio track must be at least 4 seconds long including Silent, but excluding Pause area.

Gap
The following gaps must be placed in between Data track and Audio track:
Postgap … 　When data track is followed by audio track, a 2 seconds of postgap must exist at the end of data track.
Pregap … When audio track is followed by data track, a 3 seconds of pregap must exist at the head of data track.Out of the 3 seconds, the first 1 sec is audio encode and the rest 2 seconds are data encode.
Also, at the end of track immediately before Lead Out 1, the followings must be placed:
1) For Data track: 2 seconds of Postgap.
2) For Audio track: 2 seconds of Silent area.

The System Area consists of 16 sectors at 000096H (FAD) in the Single-Density Area, and at 00B05EH (FAD) in the High-Density Area.
Boot code consisting of the System ID and Application Initial Program (AIP) are stored in the System Area. These are named Initial Program 0 (IP0) for the Single-Density Area, and Initial Program 1 (IP1) for the High-Density Area.
The System ID and Reserved data are allocated one sector in the Single-Density System Area, which contains 16 copies of this data

In the High-Density System Area, if the size of the Application Initial Program is less than 800H bytes, Initial Program 1 (IP1) can be allocated in 8 sectors. So by providing two copies of these 8 sectors, read errors can be minimized.
If the size of the Application Initial Program is greater than 800H bytes, the remaining space in the High-Density System Area is filled with Reserved data (00H)

Application Initial Program
The Application Initial Program is the program run when an application boots.
It is located immediately after the Area Code, and may be up to 4800H bytes in size.
It is executed under control of the application after the Security and Area Codes have been processed.

Volume Descriptor
The Volume Descriptor is special file information located at the head of the data area.
It complies with ISO9660, and so is located from 000A6H (FAD) in the Single-Density Area, and from 0B06EH (FAD) in the High-Density Area.
The Volume Descriptor consists of a Primary Volume Descriptor (PVD) and a Volume Descriptor set Terminator (VDT), allocated sequentially.

Primary Volume Descriptor
The Primary Volume Descriptor (PVD) specifies the volume attributes, and the locations of the root directory and Base Table Group.
The Primary Volume Descriptors for the Single- and High-Density Data Areas are named Primary Volume Descriptor 0 (PVD0) and Primary Volume Descriptor 1 (PVD1), respectively.
PVD0 is located at the head of the Single-Density Area, and PVD1 is located at the head of the High-Density Area.
Each Primary Volume Descriptor is one sector (800H bytes) in size.

Volume Descriptor set Terminator
The Volume Descriptor set Terminator (VDT) indicates the end of the Volume Descriptor.
The Volume Descriptor set Terminators for the Single- and High-Density Data Areas are named Volume Descriptor set Terminator 0 (VDT0) and Volume Descriptor set Terminator 1 (VDT1), respectively.
VDT0 is located immediately after Primary Volume Descriptor 0 (PVD0), and VDT1 is located immediately after Primary Volume Descriptor 1 (PVD1).
Each Volume Descriptor set Terminator is one sector (800H bytes) in size.

Communication Principle . The host and GD drive are connected via an ATA interface. The communication protocol uses ATA commands expanded by original commands.

SPI Outline. The SPI standard matches the KATANA GD-ROM drive and in a unique way simplifies and expands the ATAPI standard.

ATA SRST. The ATA software reset mechanism SRST (device control register, bit 2) is not used for this device.

ATA I/O Register. Communication between the device and the host occurs via the I/O register selected by the code data on the signal from the host (CS0-, CS1-, DA2, DA1, DA0, DIOR-, DIOW-). Except for the data register, all registers are read and written in byte units (8 bits). The data register is always accessed in 16-bit words.

Device Control Register. Bit 2 (SRST) of this register is the reset switch from the host, but it is not used in the current protocol. When wishing to perform a software reset, use the "Software Reset" command as defined in the SPI protocol. Bit 1 (nIEN) determines whether the host interrupt is made valid or not.

7 6 5 4 3 2 1 0
Reserved 1 SRST nIEN 0

Bit 2 (SRST): Software reset from host. The default is "0". Reset is performed when set to "1". However, because this is not used in this protocol use the "SPI Software Reset" command defined in SPI for performing a software reset.

Features register. This register normally specifies the data transfer mode, but it can also be used for Set Features parameters of the ATA command. When issuing commands accompanied by data transfer, such as CD_READ, specify in this register whether data should be transferred by PIO or DMA at the time of task file initialization.
Normal use (specify data transfer mode)
7 6 5 4 3 2 1 0
Reserve DMA

Bit 0 (DMA): Send data for command in DMA mode.

ATA Command Flow Sequence. Flow of the command for PIO data transfer to host system
This class applies to the following command.

Identify Device
Execution of this class of commands is accompanied by transfer of one or multiple data blocks from the device to the host. The following steps describe the process of PIO data transfer to the host system but the description does not encompass all the possible error conditions.

ATA Command (Task File Command). Indicates details regarding such commands out of the ATA specifications that are supported by this device.

To issue a command, the device adds any required parameters, loads the command in a suitable register in the command block, and writes the command code to the command register.
When a command is received, the device sets the BSY bit within 400 ns.

ATA commands that are accepted by the device are listed in Table Other commands are reserved and are not used.
ATA Commands
Command Code
Soft Reset 08h
Execute Device Diagnostic 90h
NOP 00h
Packet Command A0h
Identify Device A1h
Set Features EFh

Identify Device A1h
Requests information about the connected drive.
Using the Identify Device command, the host can receive information from the device. Data transfer by the Identify Device command is always conducted in the PIO mode.

Data returned by Identify Device command
Byte Content
0 Manufacturer ID
1 Model ID
2 Version ID
3-Fh Reserved
10h-1Fh Manufacturer name (16 ASCII characters)
20h-2Fh Model name (16 ASCII characters)
30h-3Fh Firmware version (16 ASCII characters)
40h-4Fh Reserved

CD Drive. CD Drive State Transition

(1) Status and CD drive state
The CD drive status can be checked with the REQ_STAT command or using the Sector Number register.
Table 4.1 CD Drive States
Status Description
State transition
Pause
Standby (drive stop)
CD playback
Seeking
Scanning
Tray is open
No disc
Read retry in progress (option)
Reading of disc TOC failed (access denied after this)
The status becomes when the disc is removed midway while it is rotating in the condition where the lid is closed.

SPI Command Flow Sequence
Packet Command Flow For PIO DATA To Host
This class includes the following commands.
· REQ_STAT
· REQ_MODE
· REQ_ERROR
· GET_TOC
· REQ_SES
· CD_READ
· CD_READ2
· GET_SCD
For execution, an unknown number of data bytes is sent from the device to the host.

DMA Command Flow
This class includes the following commands.
· CD_READ
· CD_READ2
For execution, an unknown number of data bytes is sent from the host to the device.

Non-Data Command Flow
This class includes the following commands.
· TEST_UNIT
· CD_OPEN
· CD_PLAY
· CD_SEEK
· CD_SCAN
No data transfer accompanies the issue of these commands.

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Juzgar por vosotros mismos...

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Ornia escribió:Ya me parecia a mi "mu bonito" y mu "herposo" lo de las casualidades en el mundo de la electronica y mas a este nivel, que me digas arreglar un azimut con un destornillador, cambiarle la goma a un amstrad cpc a un +3...........pero sacarte de la manga un lector funcional y un hd a puto boleo despues de ver las curradas de estos genios para usar un disco duro solo para leerlo...........lo dicho si estuviera en mi mano un ban de porvida y desterrado a una isla con un abaco, pa que trolees con los cangrejos LISTO !!!

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A mí me ha dicho por el MSN que para realizar el adaptador IDE, tan sólo ha utilizado un par de resistencias de 2w y un adaptador IDE.

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Sabes cuando va a estrar otra vez en linea?

puch666 escribió:
Ya esta en linea

Saludos